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Mercurial > hg > plan9front / sys/src/9/bcm64/mmu.c

revision 7235: b1dc95374307
parent 7217: 871931727b28
child 7238: 9fe2319844b6
     1.1--- a/sys/src/9/bcm64/mmu.c
     1.2+++ b/sys/src/9/bcm64/mmu.c
     1.3@@ -54,19 +54,47 @@ mmu0clear(uintptr *l1)
     1.4 	pe = PHYSDRAM + soc.dramsize;
     1.5 
     1.6 	if(PTLEVELS > 3)
     1.7-	for(pa = PHYSDRAM, va = KZERO; pa < pe; pa += PGLSZ(3), va += PGLSZ(3)){
     1.8-		if(PTL1X(pa, 3) != PTL1X(va, 3))
     1.9-			l1[PTL1X(pa, 3)] = 0;
    1.10+	for(pa = PHYSDRAM, va = KZERO; pa < pe; pa += PGLSZ(1), va += PGLSZ(1)){
    1.11+		if(PTL1X(pa, 1) != PTL1X(va, 1))
    1.12+			l1[PTL1X(pa, 1)] = 0;
    1.13 	}
    1.14 	if(PTLEVELS > 2)
    1.15 	for(pa = PHYSDRAM, va = KZERO; pa < pe; pa += PGLSZ(2), va += PGLSZ(2)){
    1.16 		if(PTL1X(pa, 2) != PTL1X(va, 2))
    1.17 			l1[PTL1X(pa, 2)] = 0;
    1.18 	}
    1.19+	for(pa = PHYSDRAM, va = KZERO; pa < pe; pa += PGLSZ(3), va += PGLSZ(3)){
    1.20+		if(PTL1X(pa, 3) != PTL1X(va, 3))
    1.21+			l1[PTL1X(pa, 3)] = 0;
    1.22+	}
    1.23+}
    1.24+
    1.25+void
    1.26+mmuidmap(uintptr *l1)
    1.27+{
    1.28+	uintptr va, pa, pe;
    1.29+
    1.30+	mmuswitch(nil);
    1.31+	flushtlb();
    1.32+
    1.33+	pe = PHYSDRAM + soc.dramsize;
    1.34+
    1.35 	for(pa = PHYSDRAM, va = KZERO; pa < pe; pa += PGLSZ(1), va += PGLSZ(1)){
    1.36 		if(PTL1X(pa, 1) != PTL1X(va, 1))
    1.37-			l1[PTL1X(pa, 1)] = 0;
    1.38+			l1[PTL1X(pa, 1)] = pa | PTEVALID | PTEBLOCK | PTEWRITE | PTEAF
    1.39+				 | PTEKERNEL | PTESH(SHARE_INNER);
    1.40 	}
    1.41+	if(PTLEVELS > 2)
    1.42+	for(pa = PHYSDRAM, va = KZERO; pa < pe; pa += PGLSZ(2), va += PGLSZ(2)){
    1.43+		if(PTL1X(pa, 2) != PTL1X(va, 2))
    1.44+			l1[PTL1X(pa, 2)] = PADDR(&l1[L1TABLEX(pa, 1)]) | PTEVALID | PTETABLE;
    1.45+	}
    1.46+	if(PTLEVELS > 3)
    1.47+	for(pa = PHYSDRAM, va = KZERO; pa < pe; pa += PGLSZ(3), va += PGLSZ(3)){
    1.48+		if(PTL1X(pa, 3) != PTL1X(va, 3))
    1.49+			l1[PTL1X(pa, 3)] = PADDR(&l1[L1TABLEX(pa, 2)]) | PTEVALID | PTETABLE;
    1.50+	}
    1.51+	setttbr(PADDR(&l1[L1TABLEX(0, PTLEVELS-1)]));
    1.52 }
    1.53 
    1.54 void
    1.55@@ -264,7 +292,6 @@ putmmu(uintptr va, uintptr pa, Page *pg)
    1.56 	uintptr *pte, old;
    1.57 	int s;
    1.58 
    1.59-// iprint("cpu%d: putmmu va %#p asid %d proc %lud %s\n", m->machno, va, up->asid, up->pid, up->text);
    1.60 	s = splhi();
    1.61 	while((pte = mmuwalk(va, 0)) == nil){
    1.62 		spllo();
    1.63@@ -345,7 +372,6 @@ mmuswitch(Proc *p)
    1.64 	if(allocasid(p))
    1.65 		flushasid((uvlong)p->asid<<48);
    1.66 
    1.67-// iprint("cpu%d: mmuswitch asid %d proc %lud %s\n", m->machno, p->asid, p->pid, p->text);
    1.68 	setttbr((uvlong)p->asid<<48 | PADDR(&m->mmul1[L1TABLEX(0, PTLEVELS-1)]));
    1.69 }
    1.70