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Mercurial > hg > plan9front / sys/src/9/bcm64/dat.h

changeset 7235: b1dc95374307
parent: ba62683c0e2d
child: c0e23a8829f7
author: cinap_lenrek@felloff.net
date: Mon, 13 May 2019 19:20:21 +0200
permissions: -rw-r--r--
description: bcm64: implement reboot support
1 /*
2  * Time.
3  *
4  * HZ should divide 1000 evenly, ideally.
5  * 100, 125, 200, 250 and 333 are okay.
6  */
7 #define HZ 100 /* clock frequency */
8 #define MS2HZ (1000/HZ) /* millisec per clock tick */
9 #define TK2SEC(t) ((t)/HZ) /* ticks to seconds */
10 
11 enum {
12  Mhz = 1000 * 1000,
13 };
14 
15 typedef struct Conf Conf;
16 typedef struct Confmem Confmem;
17 typedef struct FPsave FPsave;
18 typedef struct PFPU PFPU;
19 typedef struct ISAConf ISAConf;
20 typedef struct Label Label;
21 typedef struct Lock Lock;
22 typedef struct Memcache Memcache;
23 typedef struct MMMU MMMU;
24 typedef struct Mach Mach;
25 typedef struct Page Page;
26 typedef struct PhysUart PhysUart;
27 typedef struct PMMU PMMU;
28 typedef struct Proc Proc;
29 typedef u64int PTE;
30 typedef struct Soc Soc;
31 typedef struct Uart Uart;
32 typedef struct Ureg Ureg;
33 typedef uvlong Tval;
34 typedef void KMap;
35 
36 #pragma incomplete Ureg
37 
38 #define MAXSYSARG 5 /* for mount(fd, mpt, flag, arg, srv) */
39 
40 /*
41  * parameters for sysproc.c
42  */
43 #define AOUT_MAGIC (R_MAGIC)
44 
45 struct Lock
46 {
47  ulong key;
48  u32int sr;
49  uintptr pc;
50  Proc* p;
51  Mach* m;
52  int isilock;
53 };
54 
55 struct Label
56 {
57  uintptr sp;
58  uintptr pc;
59 };
60 
61 struct FPsave
62 {
63  uvlong regs[32][2];
64 
65  ulong control;
66  ulong status;
67 };
68 
69 struct PFPU
70 {
71  FPsave fpsave[1];
72 
73  int fpstate;
74 };
75 
76 enum
77 {
78  FPinit,
79  FPactive,
80  FPinactive,
81 
82  /* bits or'd with the state */
83  FPillegal= 0x100,
84 };
85 
86 struct Confmem
87 {
88  uintptr base;
89  usize npage;
90  uintptr limit;
91  uintptr kbase;
92  uintptr klimit;
93 };
94 
95 struct Conf
96 {
97  ulong nmach; /* processors */
98  ulong nproc; /* processes */
99  Confmem mem[1]; /* physical memory */
100  ulong npage; /* total physical pages of memory */
101  usize upages; /* user page pool */
102  ulong copymode; /* 0 is copy on write, 1 is copy on reference */
103  ulong ialloc; /* max interrupt time allocation in bytes */
104  ulong pipeqsize; /* size in bytes of pipe queues */
105  ulong nimage; /* number of page cache image headers */
106  ulong nswap; /* number of swap pages */
107  int nswppo; /* max # of pageouts per segment pass */
108  ulong hz; /* processor cycle freq */
109  ulong mhz;
110  int monitor; /* flag */
111 };
112 
113 /*
114  * MMU stuff in Mach.
115  */
116 struct MMMU
117 {
118  PTE* mmul1; /* l1 for this processor */
119 };
120 
121 /*
122  * MMU stuff in proc
123  */
124 #define NCOLOR 1 /* 1 level cache, don't worry about VCE's */
125 
126 struct PMMU
127 {
128  Page* mmul1;
129  Page* mmul1tail;
130 
131  Page* mmul2;
132  Page* mmul2tail;
133 
134  Page* mmufree;
135 
136  int asid;
137 
138  uintptr tpidr;
139 };
140 
141 #include "../port/portdat.h"
142 
143 struct Mach
144 {
145  int machno; /* physical id of processor */
146  uintptr splpc; /* pc of last caller to splhi */
147 
148  Proc* proc; /* current process */
149 
150  MMMU;
151  int flushmmu; /* flush current proc mmu state */
152 
153  ulong ticks; /* of the clock since boot time */
154  Label sched; /* scheduler wakeup */
155  Lock alarmlock; /* access to alarm list */
156  void* alarm; /* alarms bound to this clock */
157 
158  Proc* readied; /* for runproc */
159  ulong schedticks; /* next forced context switch */
160 
161  int cputype;
162  ulong delayloop;
163 
164  /* stats */
165  int tlbfault;
166  int tlbpurge;
167  int pfault;
168  int cs;
169  int syscall;
170  int load;
171  int intr;
172  uvlong fastclock; /* last sampled value */
173  uvlong inidle; /* time spent in idlehands() */
174  ulong spuriousintr;
175  int lastintr;
176  int ilockdepth;
177  Perf perf; /* performance counters */
178 
179  int cpumhz;
180  uvlong cpuhz; /* speed of cpu */
181  uvlong cyclefreq; /* Frequency of user readable cycle counter */
182 
183  int stack[1];
184 };
185 
186 struct
187 {
188  char machs[MAXMACH]; /* active CPUs */
189  int exiting; /* shutdown */
190 }active;
191 
192 #define MACHP(n) ((Mach*)MACHADDR(n))
193 
194 extern register Mach* m; /* R27 */
195 extern register Proc* up; /* R26 */
196 extern int normalprint;
197 
198 /*
199  * a parsed plan9.ini line
200  */
201 #define NISAOPT 8
202 
203 struct ISAConf {
204  char *type;
205  ulong port;
206  int irq;
207  ulong dma;
208  ulong mem;
209  ulong size;
210  ulong freq;
211 
212  int nopt;
213  char *opt[NISAOPT];
214 };
215 
216 /*
217  * Horrid. But the alternative is 'defined'.
218  */
219 #ifdef _DBGC_
220 #define DBGFLG (dbgflg[_DBGC_])
221 #else
222 #define DBGFLG (0)
223 #endif /* _DBGC_ */
224 
225 int vflag;
226 extern char dbgflg[256];
227 
228 #define dbgprint print /* for now */
229 
230 /*
231  * hardware info about a device
232  */
233 typedef struct {
234  ulong port;
235  int size;
236 } Devport;
237 
238 struct DevConf
239 {
240  ulong intnum; /* interrupt number */
241  char *type; /* card type, malloced */
242  int nports; /* Number of ports */
243  Devport *ports; /* The ports themselves */
244 };
245 
246 struct Soc { /* SoC dependent configuration */
247  ulong dramsize;
248  uintptr physio;
249  uintptr busdram;
250  uintptr busio;
251  uintptr armlocal;
252  u32int l1ptedramattrs;
253  u32int l2ptedramattrs;
254 };
255 extern Soc soc;
256 
257 #define BUSUNKNOWN -1
258 
259 /*
260  * GPIO
261  */
262 enum {
263  Input = 0x0,
264  Output = 0x1,
265  Alt0 = 0x4,
266  Alt1 = 0x5,
267  Alt2 = 0x6,
268  Alt3 = 0x7,
269  Alt4 = 0x3,
270  Alt5 = 0x2,
271 };