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Mercurial > hg > plan9front / changeset: bcm64: update io.h for pci express and raspberry pi 4

changeset 7316: 234f51ace8cd
parent 7315: 6e8b95bccec4
child 7317: 406bef7018a8
author: cinap_lenrek@felloff.net
date: Thu, 25 Jul 2019 09:08:35 +0200
files: sys/src/9/bcm64/io.h
description: bcm64: update io.h for pci express and raspberry pi 4
     1.1new file mode 100644
     1.2--- /dev/null
     1.3+++ b/sys/src/9/bcm64/io.h
     1.4@@ -0,0 +1,238 @@
     1.5+#include "../bcm/io.h"
     1.6+
     1.7+enum {
     1.8+	IRQgic		= 160,
     1.9+	IRQpci		= IRQgic + 20,
    1.10+	IRQether	= IRQgic + 29,
    1.11+};
    1.12+
    1.13+/*
    1.14+ * PCI
    1.15+ */
    1.16+enum {
    1.17+	BusCBUS		= 0,		/* Corollary CBUS */
    1.18+	BusCBUSII,			/* Corollary CBUS II */
    1.19+	BusEISA,			/* Extended ISA */
    1.20+	BusFUTURE,			/* IEEE Futurebus */
    1.21+	BusINTERN,			/* Internal bus */
    1.22+	BusISA,				/* Industry Standard Architecture */
    1.23+	BusMBI,				/* Multibus I */
    1.24+	BusMBII,			/* Multibus II */
    1.25+	BusMCA,				/* Micro Channel Architecture */
    1.26+	BusMPI,				/* MPI */
    1.27+	BusMPSA,			/* MPSA */
    1.28+	BusNUBUS,			/* Apple Macintosh NuBus */
    1.29+	BusPCI,				/* Peripheral Component Interconnect */
    1.30+	BusPCMCIA,			/* PC Memory Card International Association */
    1.31+	BusTC,				/* DEC TurboChannel */
    1.32+	BusVL,				/* VESA Local bus */
    1.33+	BusVME,				/* VMEbus */
    1.34+	BusXPRESS,			/* Express System Bus */
    1.35+};
    1.36+
    1.37+#define MKBUS(t,b,d,f)	(((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8))
    1.38+#define BUSFNO(tbdf)	(((tbdf)>>8)&0x07)
    1.39+#define BUSDNO(tbdf)	(((tbdf)>>11)&0x1F)
    1.40+#define BUSBNO(tbdf)	(((tbdf)>>16)&0xFF)
    1.41+#define BUSTYPE(tbdf)	((tbdf)>>24)
    1.42+#define BUSBDF(tbdf)	((tbdf)&0x00FFFF00)
    1.43+
    1.44+enum {					/* type 0 & type 1 pre-defined header */
    1.45+	PciVID		= 0x00,		/* vendor ID */
    1.46+	PciDID		= 0x02,		/* device ID */
    1.47+	PciPCR		= 0x04,		/* command */
    1.48+	PciPSR		= 0x06,		/* status */
    1.49+	PciRID		= 0x08,		/* revision ID */
    1.50+	PciCCRp		= 0x09,		/* programming interface class code */
    1.51+	PciCCRu		= 0x0A,		/* sub-class code */
    1.52+	PciCCRb		= 0x0B,		/* base class code */
    1.53+	PciCLS		= 0x0C,		/* cache line size */
    1.54+	PciLTR		= 0x0D,		/* latency timer */
    1.55+	PciHDT		= 0x0E,		/* header type */
    1.56+	PciBST		= 0x0F,		/* BIST */
    1.57+
    1.58+	PciBAR0		= 0x10,		/* base address */
    1.59+	PciBAR1		= 0x14,
    1.60+
    1.61+	PciCAP		= 0x34,		/* capabilities pointer */
    1.62+	PciINTL		= 0x3C,		/* interrupt line */
    1.63+	PciINTP		= 0x3D,		/* interrupt pin */
    1.64+};
    1.65+
    1.66+/* ccrb (base class code) values; controller types */
    1.67+enum {
    1.68+	Pcibcpci1	= 0,		/* pci 1.0; no class codes defined */
    1.69+	Pcibcstore	= 1,		/* mass storage */
    1.70+	Pcibcnet	= 2,		/* network */
    1.71+	Pcibcdisp	= 3,		/* display */
    1.72+	Pcibcmmedia	= 4,		/* multimedia */
    1.73+	Pcibcmem	= 5,		/* memory */
    1.74+	Pcibcbridge	= 6,		/* bridge */
    1.75+	Pcibccomm	= 7,		/* simple comms (e.g., serial) */
    1.76+	Pcibcbasesys	= 8,		/* base system */
    1.77+	Pcibcinput	= 9,		/* input */
    1.78+	Pcibcdock	= 0xa,		/* docking stations */
    1.79+	Pcibcproc	= 0xb,		/* processors */
    1.80+	Pcibcserial	= 0xc,		/* serial bus (e.g., USB) */
    1.81+	Pcibcwireless	= 0xd,		/* wireless */
    1.82+	Pcibcintell	= 0xe,		/* intelligent i/o */
    1.83+	Pcibcsatcom	= 0xf,		/* satellite comms */
    1.84+	Pcibccrypto	= 0x10,		/* encryption/decryption */
    1.85+	Pcibcdacq	= 0x11,		/* data acquisition & signal proc. */
    1.86+};
    1.87+
    1.88+/* ccru (sub-class code) values; common cases only */
    1.89+enum {
    1.90+	/* mass storage */
    1.91+	Pciscscsi	= 0,		/* SCSI */
    1.92+	Pciscide	= 1,		/* IDE (ATA) */
    1.93+	Pciscsata	= 6,		/* SATA */
    1.94+
    1.95+	/* network */
    1.96+	Pciscether	= 0,		/* Ethernet */
    1.97+
    1.98+	/* display */
    1.99+	Pciscvga	= 0,		/* VGA */
   1.100+	Pciscxga	= 1,		/* XGA */
   1.101+	Pcisc3d		= 2,		/* 3D */
   1.102+
   1.103+	/* bridges */
   1.104+	Pcischostpci	= 0,		/* host/pci */
   1.105+	Pciscpcicpci	= 1,		/* pci/pci */
   1.106+
   1.107+	/* simple comms */
   1.108+	Pciscserial	= 0,		/* 16450, etc. */
   1.109+	Pciscmultiser	= 1,		/* multiport serial */
   1.110+
   1.111+	/* serial bus */
   1.112+	Pciscusb	= 3,		/* USB */
   1.113+};
   1.114+
   1.115+enum {					/* type 0 pre-defined header */
   1.116+	PciCIS		= 0x28,		/* cardbus CIS pointer */
   1.117+	PciSVID		= 0x2C,		/* subsystem vendor ID */
   1.118+	PciSID		= 0x2E,		/* subsystem ID */
   1.119+	PciEBAR0	= 0x30,		/* expansion ROM base address */
   1.120+	PciMGNT		= 0x3E,		/* burst period length */
   1.121+	PciMLT		= 0x3F,		/* maximum latency between bursts */
   1.122+};
   1.123+
   1.124+enum {					/* type 1 pre-defined header */
   1.125+	PciPBN		= 0x18,		/* primary bus number */
   1.126+	PciSBN		= 0x19,		/* secondary bus number */
   1.127+	PciUBN		= 0x1A,		/* subordinate bus number */
   1.128+	PciSLTR		= 0x1B,		/* secondary latency timer */
   1.129+	PciIBR		= 0x1C,		/* I/O base */
   1.130+	PciILR		= 0x1D,		/* I/O limit */
   1.131+	PciSPSR		= 0x1E,		/* secondary status */
   1.132+	PciMBR		= 0x20,		/* memory base */
   1.133+	PciMLR		= 0x22,		/* memory limit */
   1.134+	PciPMBR		= 0x24,		/* prefetchable memory base */
   1.135+	PciPMLR		= 0x26,		/* prefetchable memory limit */
   1.136+	PciPUBR		= 0x28,		/* prefetchable base upper 32 bits */
   1.137+	PciPULR		= 0x2C,		/* prefetchable limit upper 32 bits */
   1.138+	PciIUBR		= 0x30,		/* I/O base upper 16 bits */
   1.139+	PciIULR		= 0x32,		/* I/O limit upper 16 bits */
   1.140+	PciEBAR1	= 0x28,		/* expansion ROM base address */
   1.141+	PciBCR		= 0x3E,		/* bridge control register */
   1.142+};
   1.143+
   1.144+enum {					/* type 2 pre-defined header */
   1.145+	PciCBExCA	= 0x10,
   1.146+	PciCBSPSR	= 0x16,
   1.147+	PciCBPBN	= 0x18,		/* primary bus number */
   1.148+	PciCBSBN	= 0x19,		/* secondary bus number */
   1.149+	PciCBUBN	= 0x1A,		/* subordinate bus number */
   1.150+	PciCBSLTR	= 0x1B,		/* secondary latency timer */
   1.151+	PciCBMBR0	= 0x1C,
   1.152+	PciCBMLR0	= 0x20,
   1.153+	PciCBMBR1	= 0x24,
   1.154+	PciCBMLR1	= 0x28,
   1.155+	PciCBIBR0	= 0x2C,		/* I/O base */
   1.156+	PciCBILR0	= 0x30,		/* I/O limit */
   1.157+	PciCBIBR1	= 0x34,		/* I/O base */
   1.158+	PciCBILR1	= 0x38,		/* I/O limit */
   1.159+	PciCBSVID	= 0x40,		/* subsystem vendor ID */
   1.160+	PciCBSID	= 0x42,		/* subsystem ID */
   1.161+	PciCBLMBAR	= 0x44,		/* legacy mode base address */
   1.162+};
   1.163+
   1.164+enum {
   1.165+	/* bar bits */
   1.166+	Barioaddr	= 1<<0,		/* vs. memory addr */
   1.167+	Barwidthshift	= 1,
   1.168+	Barwidthmask	= 3,
   1.169+	Barwidth32	= 0,
   1.170+	Barwidth64	= 2,
   1.171+	Barprefetch	= 1<<3,
   1.172+};
   1.173+
   1.174+enum
   1.175+{					/* command register */
   1.176+	IOen		= (1<<0),
   1.177+	MEMen		= (1<<1),
   1.178+	MASen		= (1<<2),
   1.179+	MemWrInv	= (1<<4),
   1.180+	PErrEn		= (1<<6),
   1.181+	SErrEn		= (1<<8),
   1.182+};
   1.183+
   1.184+/* capabilities */
   1.185+enum {
   1.186+	PciCapPMG       = 0x01,         /* power management */
   1.187+	PciCapAGP       = 0x02,
   1.188+	PciCapVPD       = 0x03,         /* vital product data */
   1.189+	PciCapSID       = 0x04,         /* slot id */
   1.190+	PciCapMSI       = 0x05,
   1.191+	PciCapCHS       = 0x06,         /* compact pci hot swap */
   1.192+	PciCapPCIX      = 0x07,
   1.193+	PciCapHTC       = 0x08,         /* hypertransport irq conf */
   1.194+	PciCapVND       = 0x09,         /* vendor specific information */
   1.195+	PciCapPCIe      = 0x10,
   1.196+	PciCapMSIX      = 0x11,
   1.197+	PciCapSATA      = 0x12,
   1.198+	PciCapHSW       = 0x0c,         /* hot swap */
   1.199+};
   1.200+
   1.201+typedef struct Pcidev Pcidev;
   1.202+struct Pcidev
   1.203+{
   1.204+	int	tbdf;			/* type+bus+device+function */
   1.205+	ushort	vid;			/* vendor ID */
   1.206+	ushort	did;			/* device ID */
   1.207+
   1.208+	ushort	pcr;
   1.209+
   1.210+	uchar	rid;
   1.211+	uchar	ccrp;
   1.212+	uchar	ccru;
   1.213+	uchar	ccrb;
   1.214+	uchar	cls;
   1.215+	uchar	ltr;
   1.216+
   1.217+	struct {
   1.218+		uintptr	bar;		/* base address */
   1.219+		int	size;
   1.220+	} mem[6];
   1.221+
   1.222+	uchar	intl;			/* interrupt line */
   1.223+
   1.224+	Pcidev*	list;
   1.225+	Pcidev*	link;			/* next device on this bno */
   1.226+
   1.227+	Pcidev*	parent;			/* up a bus */
   1.228+	Pcidev*	bridge;			/* down a bus */
   1.229+
   1.230+	int	pmrb;			/* power management register block */
   1.231+
   1.232+	struct {
   1.233+		uintptr	bar;
   1.234+		int	size;
   1.235+	} ioa, mema;
   1.236+};
   1.237+
   1.238+#define PCIWINDOW	0
   1.239+#define PCIWADDR(va)	(PADDR(va)+PCIWINDOW)
   1.240+
   1.241+#pragma varargck	type	"T"	int
   1.242+#pragma varargck	type	"T"	uint