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Mercurial > hg > plan9front / changeset: igfx: fix typo, initialize more lvds bits for G45, T60 testing

changeset 4206: 44b6a964ebbd
parent 4205: ddb8a41cde4f
child 4207: fa380b81e5f3
author: cinap_lenrek@felloff.net
date: Mon, 12 Jan 2015 16:40:02 +0100
files: sys/src/cmd/aux/vga/igfx.c
description: igfx: fix typo, initialize more lvds bits for G45, T60 testing
     1.1--- a/sys/src/cmd/aux/vga/igfx.c
     1.2+++ b/sys/src/cmd/aux/vga/igfx.c
     1.3@@ -304,8 +304,8 @@ devtype(Igfx *igfx)
     1.4 	switch(igfx->pci->did){
     1.5 	case 0x0166:	/* X230 */
     1.6 		return TypeIVB;
     1.7-
     1.8-	case 0x2a42:	/* X200s */
     1.9+	case 0x27a2:	/* T60 (testing) */
    1.10+	case 0x2a42:	/* X200 */
    1.11 		return TypeG45;
    1.12 	}
    1.13 	return -1;
    1.14@@ -608,10 +608,6 @@ initdpll(Igfx *igfx, int x, int freq, in
    1.15 	/* VGA Mode Disable */
    1.16 	dpll->ctrl.v |= (1<<28);
    1.17 
    1.18-	/* P1 Post Divisor */
    1.19-	dpll->ctrl.v &= ~0xFF00FF;
    1.20-	dpll->ctrl.v |= 0x10001<<(p1-1);
    1.21-
    1.22 	dpll->fp0.v &= ~(0x3f<<16);
    1.23 	dpll->fp0.v |= n << 16;
    1.24 	dpll->fp0.v &= ~(0x3f<<8);
    1.25@@ -619,7 +615,16 @@ initdpll(Igfx *igfx, int x, int freq, in
    1.26 	dpll->fp0.v &= ~(0x3f<<0);
    1.27 	dpll->fp0.v |= m2 << 0;
    1.28 
    1.29-	dpll->fp1.v = dpll->fp0.v;
    1.30+	/* FP0 P1 Post Divisor */
    1.31+	dpll->ctrl.v &= ~0xFF0000;
    1.32+	dpll->ctrl.v |=  0x010000<<(p1-1);
    1.33+
    1.34+	/* FP1 P1 Post divisor */
    1.35+	if(igfx->pci->did != 0x27a2){
    1.36+		dpll->ctrl.v &= ~0xFF;
    1.37+		dpll->ctrl.v |=  0x01<<(p1-1);
    1.38+		dpll->fp1.v = dpll->fp0.v;
    1.39+	}
    1.40 
    1.41 	return 0;
    1.42 }
    1.43@@ -776,6 +781,19 @@ init(Vga* vga, Ctlr* ctlr)
    1.44 			x = (igfx->lvds.v >> 30) & 1;
    1.45 		igfx->lvds.v |= (1<<31);
    1.46 		igfx->ppcontrol.v |= 5;
    1.47+
    1.48+		if(igfx->type == TypeG45){
    1.49+			igfx->lvds.v &= ~(1<<24);	/* data format select 18/24bpc */
    1.50+
    1.51+			igfx->lvds.v &= ~(3<<20);
    1.52+			if(m->hsync == '-')
    1.53+				igfx->lvds.v ^= 1<<20;
    1.54+			if(m->vsync == '-')
    1.55+				igfx->lvds.v ^= 1<<21;
    1.56+
    1.57+			igfx->lvds.v |= (1<<15);	/* border enable */
    1.58+		}
    1.59+
    1.60 	} else {
    1.61 		if(igfx->npipe > 2)
    1.62 			x = (igfx->adpa.v >> 29) & 3;
    1.63@@ -786,14 +804,11 @@ init(Vga* vga, Ctlr* ctlr)
    1.64 			igfx->adpa.v &= ~(3<<10);	/* Monitor DPMS: on */
    1.65 
    1.66 			igfx->adpa.v &= ~(1<<15);	/* ADPA Polarity Select */
    1.67-			if(m->vsync == '+')
    1.68-				igfx->adpa.v |= 1<<4;
    1.69-			else if(m->vsync == '-')
    1.70-				igfx->adpa.v &= ~(1<<14);
    1.71-			if(m->hsync == '+')
    1.72-				igfx->adpa.v |= 1<<3;
    1.73-			else if(m->hsync == '-')
    1.74-				igfx->adpa.v &= ~(1<<3);
    1.75+			igfx->adpa.v |= 3<<3;
    1.76+			if(m->hsync == '-')
    1.77+				igfx->adpa.v ^= 1<<3;
    1.78+			if(m->vsync == '-')
    1.79+				igfx->adpa.v ^= 1<<4;
    1.80 		}
    1.81 	}
    1.82 	p = &igfx->pipe[x];