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Mercurial > hg > plan9front / changeset: bcm, bcm64: add dmaflush() function and make virtio size and virtual address configurable in Soc.virtio and Soc.iosize

changeset 7310: 55d93e47a2de
parent 7309: 889b634159e5
child 7311: 686cdda01118
author: cinap_lenrek@felloff.net
date: Thu, 25 Jul 2019 08:41:37 +0200
files: sys/src/9/bcm/archbcm.c sys/src/9/bcm/archbcm2.c sys/src/9/bcm/dat.h sys/src/9/bcm/dma.c sys/src/9/bcm/fns.h sys/src/9/bcm/io.h sys/src/9/bcm/mmu.c sys/src/9/bcm64/archbcm3.c sys/src/9/bcm64/dat.h sys/src/9/bcm64/fns.h
description: bcm, bcm64: add dmaflush() function and make virtio size and virtual address configurable in Soc.virtio and Soc.iosize
     1.1--- a/sys/src/9/bcm/archbcm.c
     1.2+++ b/sys/src/9/bcm/archbcm.c
     1.3@@ -15,8 +15,10 @@
     1.4 
     1.5 Soc soc = {
     1.6 	.dramsize	= 512*MiB,
     1.7+	.busdram	= 0x40000000,
     1.8+	.iosize		= 16*MiB,
     1.9+	.virtio		= VIRTIO,
    1.10 	.physio		= 0x20000000,
    1.11-	.busdram	= 0x40000000,
    1.12 	.busio		= 0x7E000000,
    1.13 	.armlocal	= 0,
    1.14 	.l1ptedramattrs = Cached | Buffered,
     2.1--- a/sys/src/9/bcm/archbcm2.c
     2.2+++ b/sys/src/9/bcm/archbcm2.c
     2.3@@ -20,8 +20,10 @@ typedef struct Mboxes Mboxes;
     2.4 
     2.5 Soc soc = {
     2.6 	.dramsize	= 0x3F000000, 	/* was 1024*MiB, but overlaps with physio */
     2.7+	.busdram	= 0xC0000000,
     2.8+	.iosize		= 16*MiB,
     2.9+	.virtio		= VIRTIO,
    2.10 	.physio		= 0x3F000000,
    2.11-	.busdram	= 0xC0000000,
    2.12 	.busio		= 0x7E000000,
    2.13 	.armlocal	= 0x40000000,
    2.14 	.l1ptedramattrs = Cached | Buffered | L1wralloc | L1sharable,
     3.1--- a/sys/src/9/bcm/dat.h
     3.2+++ b/sys/src/9/bcm/dat.h
     3.3@@ -281,17 +281,17 @@ struct DevConf
     3.4 
     3.5 struct Soc {			/* SoC dependent configuration */
     3.6 	ulong	dramsize;
     3.7-	uintptr	physio;
     3.8+	ulong	iosize;
     3.9 	uintptr	busdram;
    3.10 	uintptr	busio;
    3.11+	uintptr	physio;
    3.12+	uintptr	virtio;
    3.13 	uintptr	armlocal;
    3.14 	u32int	l1ptedramattrs;
    3.15 	u32int	l2ptedramattrs;
    3.16 };
    3.17 extern Soc soc;
    3.18 
    3.19-#define BUSUNKNOWN -1
    3.20-
    3.21 /*
    3.22  * GPIO
    3.23  */
     4.1--- a/sys/src/9/bcm/dma.c
     4.2+++ b/sys/src/9/bcm/dma.c
     4.3@@ -82,6 +82,8 @@ struct Ctlr {
     4.4 	Cb	*cb;
     4.5 	Rendez	r;
     4.6 	int	dmadone;
     4.7+	void	*flush;
     4.8+	int	len;
     4.9 };
    4.10 
    4.11 struct Cb {
    4.12@@ -108,7 +110,7 @@ dmaaddr(void *va)
    4.13 static uintptr
    4.14 dmaioaddr(void *va)
    4.15 {
    4.16-	return soc.busio | ((uintptr)va - VIRTIO);
    4.17+	return soc.busio | ((uintptr)va - soc.virtio);
    4.18 }
    4.19 
    4.20 static void
    4.21@@ -164,26 +166,28 @@ dmastart(int chan, int dev, int dir, voi
    4.22 		ctlr->regs[Cs] = Reset;
    4.23 		while(ctlr->regs[Cs] & Reset)
    4.24 			;
    4.25-		intrenable(IRQDMA(chan), dmainterrupt, ctlr, 0, "dma");
    4.26+		intrenable(IRQDMA(chan), dmainterrupt, ctlr, BUSUNKNOWN, "dma");
    4.27 	}
    4.28+	ctlr->len = len;
    4.29 	cb = ctlr->cb;
    4.30 	ti = 0;
    4.31 	switch(dir){
    4.32 	case DmaD2M:
    4.33-		cachedwbinvse(dst, len);
    4.34+		ctlr->flush = dst;
    4.35 		ti = Srcdreq | Destinc;
    4.36 		cb->sourcead = dmaioaddr(src);
    4.37 		cb->destad = dmaaddr(dst);
    4.38 		break;
    4.39 	case DmaM2D:
    4.40-		cachedwbse(src, len);
    4.41+		ctlr->flush = nil;
    4.42+		dmaflush(1, src, len);
    4.43 		ti = Destdreq | Srcinc;
    4.44 		cb->sourcead = dmaaddr(src);
    4.45 		cb->destad = dmaioaddr(dst);
    4.46 		break;
    4.47 	case DmaM2M:
    4.48-		cachedwbse(src, len);
    4.49-		cachedwbinvse(dst, len);
    4.50+		ctlr->flush = dst;
    4.51+		dmaflush(1, src, len);
    4.52 		ti = Srcinc | Destinc;
    4.53 		cb->sourcead = dmaaddr(src);
    4.54 		cb->destad = dmaaddr(dst);
    4.55@@ -193,7 +197,7 @@ dmastart(int chan, int dev, int dir, voi
    4.56 	cb->txfrlen = len;
    4.57 	cb->stride = 0;
    4.58 	cb->nextconbk = 0;
    4.59-	cachedwbse(cb, sizeof(Cb));
    4.60+	dmaflush(1, cb, sizeof(Cb));
    4.61 	ctlr->regs[Cs] = 0;
    4.62 	microdelay(1);
    4.63 	ctlr->regs[Conblkad] = dmaaddr(cb);
    4.64@@ -220,6 +224,10 @@ dmawait(int chan)
    4.65 	ctlr = &dma[chan];
    4.66 	tsleep(&ctlr->r, dmadone, ctlr, 3000);
    4.67 	ctlr->dmadone = 0;
    4.68+	if(ctlr->flush != nil){
    4.69+		dmaflush(0, ctlr->flush, ctlr->len);
    4.70+		ctlr->flush = nil;
    4.71+	}
    4.72 	r = ctlr->regs;
    4.73 	DBG dumpdregs("after sleep", r);
    4.74 	s = r[Cs];
    4.75@@ -233,3 +241,31 @@ dmawait(int chan)
    4.76 	r[Cs] = Int|End;
    4.77 	return 0;
    4.78 }
    4.79+
    4.80+void
    4.81+dmaflush(int clean, void *p, ulong len)
    4.82+{
    4.83+	uintptr s = (uintptr)p;
    4.84+	uintptr e = (uintptr)p + len;
    4.85+
    4.86+	if(clean){
    4.87+		s &= ~(BLOCKALIGN-1);
    4.88+		e += BLOCKALIGN-1;
    4.89+		e &= ~(BLOCKALIGN-1);
    4.90+		cachedwbse((void*)s, e - s);
    4.91+		return;
    4.92+	}
    4.93+	if(s & BLOCKALIGN-1){
    4.94+		s &= ~(BLOCKALIGN-1);
    4.95+		cachedwbinvse((void*)s, BLOCKALIGN);
    4.96+		s += BLOCKALIGN;
    4.97+	}
    4.98+	if(e & BLOCKALIGN-1){
    4.99+		e &= ~(BLOCKALIGN-1);
   4.100+		if(e < s)
   4.101+			return;
   4.102+		cachedwbinvse((void*)e, BLOCKALIGN);
   4.103+	}
   4.104+	if(s < e)
   4.105+		cachedinvse((void*)s, e - s);
   4.106+}
     5.1--- a/sys/src/9/bcm/fns.h
     5.2+++ b/sys/src/9/bcm/fns.h
     5.3@@ -28,6 +28,7 @@ extern u32int cpidget(void);
     5.4 extern void cpwr(int cp, int op1, int crn, int crm, int op2, ulong val);
     5.5 extern void cpwrsc(int op1, int crn, int crm, int op2, ulong val);
     5.6 #define cycles(ip) *(ip) = lcycles()
     5.7+extern void dmaflush(int, void*, ulong);
     5.8 extern void dmastart(int, int, int, void*, void*, int);
     5.9 extern int dmawait(int);
    5.10 extern uintptr dmaaddr(void *va);
     6.1--- a/sys/src/9/bcm/io.h
     6.2+++ b/sys/src/9/bcm/io.h
     6.3@@ -63,3 +63,5 @@ enum {
     6.4 	ClkPixel,
     6.5 	ClkPwm,
     6.6 };
     6.7+
     6.8+#define BUSUNKNOWN (-1)
     7.1--- a/sys/src/9/bcm/mmu.c
     7.2+++ b/sys/src/9/bcm/mmu.c
     7.3@@ -49,8 +49,8 @@ mmuinit(void *a)
     7.4 	/*
     7.5 	 * map i/o registers 
     7.6 	 */
     7.7-	va = VIRTIO;
     7.8-	for(pa = soc.physio; pa < soc.physio+IOSIZE; pa += MiB){
     7.9+	va = soc.virtio;
    7.10+	for(pa = soc.physio; pa < soc.physio+soc.iosize; pa += MiB){
    7.11 		l1[L1X(va)] = pa|Dom0|L1AP(Krw)|Section;
    7.12 		va += MiB;
    7.13 	}
    7.14@@ -305,7 +305,7 @@ uintptr
    7.15 cankaddr(uintptr pa)
    7.16 {
    7.17 	if(pa < PHYSDRAM+soc.dramsize)
    7.18-		return PHYSDRAM+soc.dramsize - pa;
    7.19+		return ((uintptr)PHYSDRAM+soc.dramsize) - pa;
    7.20 	return 0;
    7.21 }
    7.22 
     8.1--- a/sys/src/9/bcm64/archbcm3.c
     8.2+++ b/sys/src/9/bcm64/archbcm3.c
     8.3@@ -17,10 +17,12 @@ typedef struct Mboxes Mboxes;
     8.4 #define	POWERREGS	(VIRTIO+0x100000)
     8.5 
     8.6 Soc soc = {
     8.7-	.dramsize	= 0x3F000000,
     8.8+	.dramsize	= 0x3E000000,
     8.9+	.busdram	= 0xC0000000,
    8.10+	.iosize		= 0x01000000,
    8.11+	.busio		= 0x7E000000,
    8.12 	.physio		= 0x3F000000,
    8.13-	.busdram	= 0xC0000000,
    8.14-	.busio		= 0x7E000000,
    8.15+	.virtio		= VIRTIO,
    8.16 	.armlocal	= 0x40000000,
    8.17 };
    8.18 
    8.19@@ -164,5 +166,5 @@ wakecpu(uint cpu)
    8.20 void
    8.21 archbcm3link(void)
    8.22 {
    8.23-	addclock0link(wdogfeed, HZ);
    8.24+	// addclock0link(wdogfeed, HZ);
    8.25 }
     9.1--- a/sys/src/9/bcm64/dat.h
     9.2+++ b/sys/src/9/bcm64/dat.h
     9.3@@ -241,15 +241,16 @@ struct DevConf
     9.4 
     9.5 struct Soc {			/* SoC dependent configuration */
     9.6 	ulong	dramsize;
     9.7+	uintptr	busdram;
     9.8+	ulong	iosize;
     9.9+	uintptr	busio;
    9.10 	uintptr	physio;
    9.11-	uintptr	busdram;
    9.12-	uintptr	busio;
    9.13+	uintptr	virtio;
    9.14 	uintptr	armlocal;
    9.15+	uintptr	pciwin;
    9.16 };
    9.17 extern Soc soc;
    9.18 
    9.19-#define BUSUNKNOWN -1
    9.20-
    9.21 /*
    9.22  * GPIO
    9.23  */
    10.1--- a/sys/src/9/bcm64/fns.h
    10.2+++ b/sys/src/9/bcm64/fns.h
    10.3@@ -144,6 +144,7 @@ extern void wdogoff(void);
    10.4 
    10.5 /* dma */
    10.6 extern uintptr dmaaddr(void*);
    10.7+extern void dmaflush(int, void*, ulong);
    10.8 extern void dmastart(int, int, int, void*, void*, int);
    10.9 extern int dmawait(int);
   10.10