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Mercurial > hg > plan9front / changeset: bcm: simplify reboot code

changeset 6851: 817828d0da99
parent 6850: c3a500ff9c5f
child 6852: c775e38cca81
author: cinap_lenrek@felloff.net
date: Sun, 28 Oct 2018 06:16:10 +0100
files: sys/src/9/bcm/archbcm2.c sys/src/9/bcm/arm.s sys/src/9/bcm/armv7.s sys/src/9/bcm/fns.h sys/src/9/bcm/main.c sys/src/9/bcm/mem.h sys/src/9/bcm/mkfile sys/src/9/bcm/mmu.c sys/src/9/bcm/rebootcode.s
description: bcm: simplify reboot code

- synchronize rebootcode installation
- handle the 1MB identity map in mmu.c (mmuinit1())
- do not overlap CONFADDR with rebootcode, the non boot
processors are parked there.
- make REBOOTADDR physical address
     1.1--- a/sys/src/9/bcm/archbcm2.c
     1.2+++ b/sys/src/9/bcm/archbcm2.c
     1.3@@ -237,7 +237,7 @@ cpustart(int cpu)
     1.4 	mb->clr[cpu].doorbell = 1;
     1.5 	trapinit();
     1.6 	clockinit();
     1.7-	mmuinit1();
     1.8+	mmuinit1(0);
     1.9 	timersinit();
    1.10 	cpuidprint();
    1.11 	archreset();
     2.1--- a/sys/src/9/bcm/arm.s
     2.2+++ b/sys/src/9/bcm/arm.s
     2.3@@ -40,8 +40,6 @@
     2.4 	MOVW	$0x10000,R3; \
     2.5 	MOVW	R3,(R2)
     2.6 
     2.7-#define PUTC(s)
     2.8-
     2.9 /*
    2.10  * get cpu id, or zero if armv6
    2.11  */
     3.1--- a/sys/src/9/bcm/armv7.s
     3.2+++ b/sys/src/9/bcm/armv7.s
     3.3@@ -46,6 +46,17 @@ TEXT armstart(SB), 1, $-4
     3.4 	BARRIERS
     3.5 
     3.6 	/*
     3.7+	 * turn SMP on
     3.8+	 * invalidate tlb
     3.9+	 */
    3.10+	MRC	CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
    3.11+	ORR	$CpACsmp, R1		/* turn SMP on */
    3.12+	MCR	CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
    3.13+	BARRIERS
    3.14+	MCR	CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
    3.15+	BARRIERS
    3.16+
    3.17+	/*
    3.18 	 * clear mach and page tables
    3.19 	 */
    3.20 	MOVW	$PADDR(MACHADDR), R1
    3.21@@ -57,17 +68,6 @@ TEXT armstart(SB), 1, $-4
    3.22 	BNE	_ramZ
    3.23 
    3.24 	/*
    3.25-	 * turn SMP on
    3.26-	 * invalidate tlb
    3.27-	 */
    3.28-	MRC	CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
    3.29-	ORR	$CpACsmp, R1		/* turn SMP on */
    3.30-	MCR	CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
    3.31-	BARRIERS
    3.32-	MCR	CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
    3.33-	BARRIERS
    3.34-
    3.35-	/*
    3.36 	 * start stack at top of mach (physical addr)
    3.37 	 * set up page tables for kernel
    3.38 	 */
    3.39@@ -96,7 +96,6 @@ TEXT armstart(SB), 1, $-4
    3.40 	/*
    3.41 	 * enable caches, mmu, and high vectors
    3.42 	 */
    3.43-
    3.44 	MRC	CpSC, 0, R0, C(CpCONTROL), C(0), CpMainctl
    3.45 	ORR	$(CpChv|CpCdcache|CpCicache|CpCmmu), R0
    3.46 	MCR	CpSC, 0, R0, C(CpCONTROL), C(0), CpMainctl
     4.1--- a/sys/src/9/bcm/fns.h
     4.2+++ b/sys/src/9/bcm/fns.h
     4.3@@ -66,7 +66,7 @@ extern int isaconfig(char*, int, ISAConf
     4.4 extern void l2cacheuwbinv(void);
     4.5 extern void links(void);
     4.6 extern void mmuinit(void*);
     4.7-extern void mmuinit1(void);
     4.8+extern void mmuinit1(int);
     4.9 extern void mmuinvalidate(void);
    4.10 extern void mmuinvalidateaddr(u32int);
    4.11 extern uintptr mmukmap(uintptr, uintptr, usize);
     5.1--- a/sys/src/9/bcm/main.c
     5.2+++ b/sys/src/9/bcm/main.c
     5.3@@ -19,7 +19,7 @@
     5.4  * Where configuration info is left for the loaded programme.
     5.5  */
     5.6 #define BOOTARGS	((char*)CONFADDR)
     5.7-#define	BOOTARGSLEN	(MACHADDR-CONFADDR)
     5.8+#define	BOOTARGSLEN	(REBOOTADDR-PADDR(CONFADDR))
     5.9 #define	MAXCONF		64
    5.10 #define MAXCONFLINE	160
    5.11 
    5.12@@ -301,7 +301,7 @@ main(void)
    5.13 	pageinit();
    5.14 	userinit();
    5.15 	launchinit();
    5.16-	mmuinit1();
    5.17+	mmuinit1(0);
    5.18 	schedinit();
    5.19 	assert(0);			/* shouldn't have returned */
    5.20 }
    5.21@@ -550,6 +550,35 @@ confinit(void)
    5.22 
    5.23 }
    5.24 
    5.25+static void
    5.26+rebootjump(ulong entry, ulong code, ulong size)
    5.27+{
    5.28+	static void (*f)(ulong, ulong, ulong);
    5.29+	static Lock lk;
    5.30+
    5.31+	intrsoff();
    5.32+	intrcpushutdown();
    5.33+
    5.34+	/* redo identity map */
    5.35+	mmuinit1(1);
    5.36+
    5.37+	lock(&lk);
    5.38+	if(f == nil){
    5.39+		/* setup reboot trampoline function */
    5.40+		f = (void*)REBOOTADDR;
    5.41+		memmove(f, rebootcode, sizeof(rebootcode));
    5.42+		cachedwbse(f, sizeof(rebootcode));
    5.43+	}
    5.44+	unlock(&lk);
    5.45+
    5.46+	cacheuwbinv();
    5.47+	l2cacheuwbinv();
    5.48+
    5.49+	(*f)(entry, code, size);
    5.50+
    5.51+	for(;;);
    5.52+}
    5.53+
    5.54 /*
    5.55  *  exit kernel either on a panic or user request
    5.56  */
    5.57@@ -558,14 +587,8 @@ exit(int)
    5.58 {
    5.59 	cpushutdown();
    5.60 	splfhi();
    5.61-	if(m->machno != 0){
    5.62-		void (*f)(ulong, ulong, ulong) = (void*)REBOOTADDR;
    5.63-		intrsoff();
    5.64-		intrcpushutdown();
    5.65-		cacheuwbinv();
    5.66-		(*f)(0, 0, 0);
    5.67-		for(;;);
    5.68-	}
    5.69+	if(m->machno != 0)
    5.70+		rebootjump(0, 0, 0);
    5.71 	archreboot();
    5.72 }
    5.73 
    5.74@@ -585,21 +608,14 @@ isaconfig(char *, int, ISAConf *)
    5.75 void
    5.76 reboot(void *entry, void *code, ulong size)
    5.77 {
    5.78-	void (*f)(ulong, ulong, ulong);
    5.79-
    5.80 	writeconf();
    5.81 	if (m->machno != 0) {
    5.82 		procwired(up, 0);
    5.83 		sched();
    5.84 	}
    5.85 
    5.86-	/* setup reboot trampoline function */
    5.87-	f = (void*)REBOOTADDR;
    5.88-	memmove(f, rebootcode, sizeof(rebootcode));
    5.89-	cachedwbse(f, sizeof(rebootcode));
    5.90-
    5.91 	cpushutdown();
    5.92-	delay(500);
    5.93+	delay(1000);
    5.94 
    5.95 	splfhi();
    5.96 
    5.97@@ -611,14 +627,10 @@ reboot(void *entry, void *code, ulong si
    5.98 
    5.99 	/* stop the clock (and watchdog if any) */
   5.100 	clockshutdown();
   5.101-	intrsoff();
   5.102-	intrcpushutdown();
   5.103-
   5.104-	cacheuwbinv();
   5.105-	l2cacheuwbinv();
   5.106+	wdogoff();
   5.107 
   5.108 	/* off we go - never to return */
   5.109-	(*f)(PADDR(entry), PADDR(code), size);
   5.110+	rebootjump(PADDR(entry), PADDR(code), size);
   5.111 }
   5.112 
   5.113 void
     6.1--- a/sys/src/9/bcm/mem.h
     6.2+++ b/sys/src/9/bcm/mem.h
     6.3@@ -44,6 +44,7 @@
     6.4 #define	KSEGM		0xC0000000
     6.5 #define	KZERO		KSEG0			/* kernel address space */
     6.6 #define CONFADDR	(KZERO+0x100)		/* unparsed plan9.ini */
     6.7+#define	REBOOTADDR	(0x1c00)		/* reboot code - physical address */
     6.8 #define	MACHADDR	(KZERO+0x2000)		/* Mach structure */
     6.9 #define	L2		(KZERO+0x3000)		/* L2 ptes for vectors etc */
    6.10 #define	VCBUFFER	(KZERO+0x3400)		/* videocore mailbox buffer */
    6.11@@ -62,9 +63,6 @@
    6.12 #define	TSTKTOP		(USTKTOP-USTKSIZE)	/* sysexec temporary stack */
    6.13 #define	TSTKSIZ	 	256
    6.14 
    6.15-/* address at which to copy and execute rebootcode */
    6.16-#define	REBOOTADDR	(KZERO+0x1800)
    6.17-
    6.18 /*
    6.19  * Legacy...
    6.20  */
     7.1--- a/sys/src/9/bcm/mkfile
     7.2+++ b/sys/src/9/bcm/mkfile
     7.3@@ -123,8 +123,8 @@ init.h:D:	../port/initcode.c init9.s
     7.4 
     7.5 reboot.h:D:	rebootcode.s arm.s arm.h mem.h
     7.6 	$AS rebootcode.s
     7.7-	# -lc is only for memmove.  -T arg is PADDR(REBOOTADDR)
     7.8-	$LD -l -s -T0x1800 -R4 -o reboot.out rebootcode.$O -lc
     7.9+	# -lc is only for memmove.  -T arg is REBOOTADDR
    7.10+	$LD -l -s -T0x1c00 -R4 -o reboot.out rebootcode.$O -lc
    7.11 	{echo 'uchar rebootcode[]={'
    7.12 	 xd -1x reboot.out |
    7.13 		sed -e '1,2d' -e 's/^[0-9a-f]+ //' -e 's/ ([0-9a-f][0-9a-f])/0x\1,/g'
     8.1--- a/sys/src/9/bcm/mmu.c
     8.2+++ b/sys/src/9/bcm/mmu.c
     8.3@@ -12,6 +12,7 @@
     8.4 #define L2AP(ap)	l2ap(ap)
     8.5 #define L1ptedramattrs	soc.l1ptedramattrs
     8.6 #define L2ptedramattrs	soc.l2ptedramattrs
     8.7+#define PTEDRAM		(PHYSDRAM|Dom0|L1AP(Krw)|Section|L1ptedramattrs)
     8.8 
     8.9 enum {
    8.10 	L1lo		= UZERO/MiB,		/* L1X(UZERO)? */
    8.11@@ -43,7 +44,7 @@ mmuinit(void *a)
    8.12 	/*
    8.13 	 * identity map first MB of ram so mmu can be enabled
    8.14 	 */
    8.15-	l1[L1X(PHYSDRAM)] = PHYSDRAM|Dom0|L1AP(Krw)|Section|L1ptedramattrs;
    8.16+	l1[L1X(PHYSDRAM)] = PTEDRAM;
    8.17 
    8.18 	/*
    8.19 	 * map i/o registers 
    8.20@@ -65,19 +66,19 @@ mmuinit(void *a)
    8.21 	l2[L2X(va)] = PHYSDRAM|L2AP(Krw)|Small|L2ptedramattrs;
    8.22 }
    8.23 
    8.24+/*
    8.25+ * enable/disable identity map of first MB of ram
    8.26+ */
    8.27 void
    8.28-mmuinit1()
    8.29+mmuinit1(int on)
    8.30 {
    8.31 	PTE *l1;
    8.32 
    8.33 	l1 = m->mmul1;
    8.34-
    8.35-	/*
    8.36-	 * undo identity map of first MB of ram
    8.37-	 */
    8.38-	l1[L1X(PHYSDRAM)] = 0;
    8.39+	l1[L1X(PHYSDRAM)] = on? PTEDRAM: Fault;
    8.40 	cachedwbtlb(&l1[L1X(PHYSDRAM)], sizeof(PTE));
    8.41 	mmuinvalidateaddr(PHYSDRAM);
    8.42+	mmuinvalidate();
    8.43 }
    8.44 
    8.45 static void
     9.1--- a/sys/src/9/bcm/rebootcode.s
     9.2+++ b/sys/src/9/bcm/rebootcode.s
     9.3@@ -3,8 +3,6 @@
     9.4  */
     9.5 #include "arm.s"
     9.6 
     9.7-#define PTEDRAM		(Dom0|L1AP(Krw)|Section)
     9.8-
     9.9 #define WFI	WORD	$0xe320f003	/* wait for interrupt */
    9.10 #define WFE	WORD	$0xe320f002	/* wait for event */
    9.11 
    9.12@@ -26,8 +24,16 @@ TEXT	main(SB), 1, $-4
    9.13 	MOVW	$(PsrDirq|PsrDfiq|PsrMsvc), R1
    9.14 	MOVW	R1, CPSR
    9.15 
    9.16-	/* prepare to turn off mmu  */
    9.17-	BL	cachesoff(SB)
    9.18+	/* turn caches off */
    9.19+	MRC	CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
    9.20+	BIC	$(CpCdcache|CpCicache|CpCpredict), R1
    9.21+	MCR	CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
    9.22+	BARRIERS
    9.23+
    9.24+	/* invalidate icache */
    9.25+	MOVW	$0, R0
    9.26+	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
    9.27+	BARRIERS
    9.28 
    9.29 	/* turn off mmu */
    9.30 	MRC	CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
    9.31@@ -49,7 +55,7 @@ dowfi:
    9.32 	MOVW	$0x40000060, R1
    9.33 	ADD		R2<<2, R1
    9.34 	MOVW	0(R1), R0
    9.35-	AND		$0x10, R0
    9.36+	AND	$0x10, R0
    9.37 	BEQ		dowfi
    9.38 	MOVW	$0x8000, R1
    9.39 	BL		(R1)
    9.40@@ -72,47 +78,3 @@ bootcpu:
    9.41 	ORR	R8,R8
    9.42 	B	(R8)
    9.43 	B	0(PC)
    9.44-
    9.45-/*
    9.46- * turn the caches off, double map PHYSDRAM & KZERO, invalidate TLBs, revert
    9.47- * to tiny addresses.  upon return, it will be safe to turn off the mmu.
    9.48- * clobbers R0-R2, and returns with SP invalid.
    9.49- */
    9.50-TEXT cachesoff(SB), 1, $-4
    9.51-	MOVM.DB.W [R14,R1-R10], (R13)		/* save regs on stack */
    9.52-
    9.53-	/* turn caches off, invalidate icache */
    9.54-	MRC	CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
    9.55-	BIC	$(CpCdcache|CpCicache|CpCpredict), R1
    9.56-	MCR	CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
    9.57-	MOVW	$0, R0
    9.58-	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
    9.59-
    9.60-	/* invalidate stale TLBs before changing them */
    9.61-	BARRIERS
    9.62-	MOVW	$0, R0
    9.63-	MCR	CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
    9.64-	BARRIERS
    9.65-
    9.66-	/* redo double map of first MiB PHYSDRAM = KZERO */
    9.67-	MOVW	12(R(MACH)), R2		/* m->mmul1 (virtual addr) */
    9.68-	MOVW	$PTEDRAM, R1			/* PTE bits */
    9.69-	MOVW	R1, (R2)
    9.70-	DSB
    9.71-	MCR	CpSC, 0, R2, C(CpCACHE), C(CpCACHEwb), CpCACHEse
    9.72-
    9.73-	/* invalidate stale TLBs again */
    9.74-	BARRIERS
    9.75-	MOVW	$0, R0
    9.76-	MCR	CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
    9.77-	BARRIERS
    9.78-
    9.79-	/* relocate SB and return address to PHYSDRAM addressing */
    9.80-	MOVW	$KSEGM, R1		/* clear segment bits */
    9.81-	BIC	R1, R12			/* adjust SB */
    9.82-	MOVM.IA.W (R13), [R14,R1-R10]		/* restore regs from stack */
    9.83-
    9.84-	MOVW	$KSEGM, R1		/* clear segment bits */
    9.85-	BIC	R1, R14			/* adjust return address */
    9.86-
    9.87-	RET