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Mercurial > hg > plan9front / changeset: bcm: move fiq saved pc adjust into lexception.s so it can be shared with arm64

changeset 7197: babef06a3de5
parent 7196: 9a4da3139862
child 7198: bee572b18071
author: cinap_lenrek@felloff.net
date: Fri, 03 May 2019 22:02:07 +0200
files: sys/src/9/bcm/irq.c sys/src/9/bcm/lexception.s sys/src/9/bcm/trap.c
description: bcm: move fiq saved pc adjust into lexception.s so it can be shared with arm64
     1.1--- a/sys/src/9/bcm/irq.c
     1.2+++ b/sys/src/9/bcm/irq.c
     1.3@@ -83,6 +83,7 @@ irq(Ureg* ureg)
     1.4 	Vctl *v;
     1.5 	int clockintr;
     1.6 
     1.7+	m->intr++;
     1.8 	clockintr = 0;
     1.9 	for(v = vctl[m->machno]; v != nil; v = v->next)
    1.10 		if((*v->reg & v->mask) != 0){
    1.11@@ -103,11 +104,10 @@ fiq(Ureg *ureg)
    1.12 {
    1.13 	Vctl *v;
    1.14 
    1.15+	m->intr++;
    1.16 	v = vfiq;
    1.17 	if(v == nil)
    1.18 		panic("cpu%d: unexpected item in bagging area", m->machno);
    1.19-	m->intr++;
    1.20-	ureg->pc -= 4;
    1.21 	coherence();
    1.22 	v->f(ureg, v->a);
    1.23 	coherence();
     2.1--- a/sys/src/9/bcm/lexception.s
     2.2+++ b/sys/src/9/bcm/lexception.s
     2.3@@ -187,6 +187,7 @@ TEXT _vfiq(SB), 1, $-4			/* FIQ */
     2.4 	MOVW	$PsrMfiq, R8		/* trap type */
     2.5 	MOVW	SPSR, R9		/* interrupted psr */
     2.6 	MOVW	R14, R10		/* interrupted pc */
     2.7+	SUB	$4, R10			/* ureg->pc -= 4 */
     2.8 	MOVM.DB.W [R8-R10], (R13)	/* save in ureg */
     2.9 	MOVM.DB.S [R0-R14], (R13)	/* save interrupted regs */
    2.10 	SUB	$(15*4), R13
     3.1--- a/sys/src/9/bcm/trap.c
     3.2+++ b/sys/src/9/bcm/trap.c
     3.3@@ -188,7 +188,6 @@ trap(Ureg *ureg)
     3.4 		break;
     3.5 	case PsrMirq:
     3.6 		clockintr = irq(ureg);
     3.7-		m->intr++;
     3.8 		break;
     3.9 	case PsrMabt:			/* prefetch fault */
    3.10 		x = ifsrget();