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Mercurial > hg > plan9front / sys/src/9/bcm64/mem.h

changeset 7217: 871931727b28
parent: ba62683c0e2d
child: 2e8af1bf191d
author: cinap_lenrek@felloff.net
date: Thu, 09 May 2019 02:17:50 +0200
permissions: -rw-r--r--
description: bcm64: map framebuffer write-through to allow unaligned access
1 /*
2  * Memory and machine-specific definitions. Used in C and assembler.
3  */
4 #define KiB 1024u /* Kibi 0x0000000000000400 */
5 #define MiB 1048576u /* Mebi 0x0000000000100000 */
6 #define GiB 1073741824u /* Gibi 000000000040000000 */
7 
8 #define HOWMANY(x,y) (((x)+((y)-1))/(y))
9 #define ROUNDUP(x,y) (HOWMANY((x),(y))*(y))
10 #define PGROUND(s) ROUNDUP(s, BY2PG)
11 #define ROUND(s, sz) (((s)+(sz-1))&~(sz-1))
12 
13 /*
14  * Sizes:
15  * L0 L1 L2 L3
16  * 4K 2M 1G 512G
17  * 16K 32M 64G 128T
18  * 64K 512M 4T -
19  */
20 #define PGSHIFT 12 /* log(BY2PG) */
21 #define BY2PG (1ULL<<PGSHIFT) /* bytes per page */
22 
23 /* effective virtual address space */
24 #define EVASHIFT 36
25 #define EVAMASK ((1ULL<<EVASHIFT)-1)
26 
27 #define PTSHIFT (PGSHIFT-3)
28 #define PTLEVELS HOWMANY(EVASHIFT-PGSHIFT, PTSHIFT)
29 #define PTLX(v, l) ((((v) & EVAMASK) >> (PGSHIFT + (l)*PTSHIFT)) & ((1 << PTSHIFT)-1))
30 #define PGLSZ(l) (1ULL << (PGSHIFT + (l)*PTSHIFT))
31 
32 #define PTL1X(v, l) (L1TABLEX(v, l) | PTLX(v, l))
33 #define L1TABLEX(v, l) (L1TABLE(v, l) << PTSHIFT)
34 #define L1TABLES HOWMANY(-KZERO, PGLSZ(2))
35 #define L1TABLE(v, l) (L1TABLES-1 - ((PTLX(v, 2) % L1TABLES) >> (((l)-1)*PTSHIFT)) + (l)-1)
36 #define L1TOPSIZE (1ULL << (EVASHIFT - PTLEVELS*PTSHIFT))
37 
38 #define MAXMACH 4 /* max # cpus system can run */
39 #define MACHSIZE (8*KiB)
40 
41 #define KSTACK (8*KiB)
42 #define STACKALIGN(sp) ((sp) & ~7) /* bug: assure with alloc */
43 #define TRAPFRAMESIZE (38*8)
44 
45 /*
46  * Address spaces.
47  * KTZERO is used by kprof and dumpstack (if any).
48  *
49  * KZERO is mapped to physical 0 (start of ram).
50  */
51 
52 #define KZERO 0xFFFFFFFF80000000ULL /* kernel address space */
53 
54 #define SPINTABLE (KZERO+0xd8)
55 #define CONFADDR (KZERO+0x100)
56 #define REBOOTADDR (0x1c00) /* reboot code - physical address */
57 #define VCBUFFER (KZERO+0x3400) /* videocore mailbox buffer */
58 
59 #define L1 (L1TOP-L1SIZE)
60 #define L1SIZE ((L1TABLES+PTLEVELS-3)*BY2PG)
61 #define L1TOP ((MACHADDR(MAXMACH-1)-L1TOPSIZE)&-BY2PG)
62 
63 #define MACHADDR(n) (KTZERO-((n)+1)*MACHSIZE)
64 
65 #define KTZERO (KZERO+0x80000) /* kernel text start */
66 #define FRAMEBUFFER (0xFFFFFFFFC0000000ULL | PTEWT)
67 #define VIRTIO 0xFFFFFFFFE0000000ULL /* i/o registers */
68 #define ARMLOCAL (VIRTIO+IOSIZE)
69 #define VGPIO 0 /* virtual gpio for pi3 ACT LED */
70 
71 #define UZERO 0ULL /* user segment */
72 #define UTZERO (UZERO+0x10000) /* user text start */
73 #define USTKTOP ((EVAMASK>>1)-0xFFFF) /* user segment end +1 */
74 #define USTKSIZE (16*1024*1024) /* user stack size */
75 
76 #define BLOCKALIGN 64 /* only used in allocb.c */
77 
78 /*
79  * Sizes
80  */
81 #define BI2BY 8 /* bits per byte */
82 #define BY2SE 4
83 #define BY2WD 8
84 #define BY2V 8 /* only used in xalloc.c */
85 
86 #define PTEMAPMEM (1024*1024)
87 #define PTEPERTAB (PTEMAPMEM/BY2PG)
88 #define SEGMAPSIZE 1984
89 #define SSEGMAPSIZE 16
90 #define PPN(x) ((x)&~(BY2PG-1))
91 
92 #define SHARE_NONE 0
93 #define SHARE_OUTER 2
94 #define SHARE_INNER 3
95 
96 #define CACHE_UC 0
97 #define CACHE_WB 1
98 #define CACHE_WT 2
99 #define CACHE_WB_NA 3
100 
101 #define MA_MEM_WB 0
102 #define MA_MEM_WT 1
103 #define MA_MEM_UC 2
104 #define MA_DEV_nGnRnE 3
105 #define MA_DEV_nGnRE 4
106 #define MA_DEV_nGRE 5
107 #define MA_DEV_GRE 6
108 
109 #define PTEVALID 1
110 #define PTEBLOCK 0
111 #define PTETABLE 2
112 #define PTEPAGE 2
113 
114 #define PTEMA(x) ((x)<<2)
115 #define PTEAP(x) ((x)<<6)
116 #define PTESH(x) ((x)<<8)
117 
118 #define PTEAF (1<<10)
119 #define PTENG (1<<11)
120 
121 #define PTEKERNEL PTEAP(0)
122 #define PTEUSER PTEAP(1)
123 #define PTEWRITE PTEAP(0)
124 #define PTERONLY PTEAP(2)
125 
126 #define PTEWT PTEMA(MA_MEM_WT)
127 #define PTEUNCACHED PTEMA(MA_MEM_UC)
128 #define PTEDEVICE PTEMA(MA_DEV_nGnRE)
129 
130 /*
131  * Physical machine information from here on.
132  * PHYS addresses as seen from the arm cpu.
133  * BUS addresses as seen from the videocore gpu.
134  */
135 #define PHYSDRAM 0
136 #define IOSIZE (16*MiB)
137 
138 #define MIN(a, b) ((a) < (b)? (a): (b))
139 #define MAX(a, b) ((a) > (b)? (a): (b))