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Mercurial > hg > plan9front / changeset: bcm64: enter page tables in mmutop *AFTER* switching asid in mmuswitch()

changeset 7387: 27f7b5d5b78a
parent 7386: c2b1522cb6c7
child 7388: 5b77fd83cf2e
author: cinap_lenrek@felloff.net
date: Sat, 14 Sep 2019 14:02:34 +0200
files: sys/src/9/bcm64/mmu.c
description: bcm64: enter page tables in mmutop *AFTER* switching asid in mmuswitch()

there was a small window between modifying mmutop and switching the
asid where the core could bring in the new entries under the old asid
into the tlb due to speculation / prefetching.

this change moves the entering of the page tables into mmutop after
setttbr() to prevent this scenario.

due to us switching to the resereved asid 0 on procsave()->putasid(),
the only asid that could have potentially been poisoned would be asid 0
which does not have any user mappings. so this did not show any noticable
effect.
     1.1--- a/sys/src/9/bcm64/mmu.c
     1.2+++ b/sys/src/9/bcm64/mmu.c
     1.3@@ -499,15 +499,15 @@ mmuswitch(Proc *p)
     1.4 		p->newtlb = 0;
     1.5 	}
     1.6 
     1.7+	if(allocasid(p))
     1.8+		flushasid((uvlong)p->asid<<48);
     1.9+
    1.10+	setttbr((uvlong)p->asid<<48 | PADDR(m->mmutop));
    1.11+
    1.12 	for(t = p->mmuhead[PTLEVELS-1]; t != nil; t = t->next){
    1.13 		va = t->va;
    1.14 		m->mmutop[PTLX(va, PTLEVELS-1)] = t->pa | PTEVALID | PTETABLE;
    1.15 	}
    1.16-
    1.17-	if(allocasid(p))
    1.18-		flushasid((uvlong)p->asid<<48);
    1.19-
    1.20-	setttbr((uvlong)p->asid<<48 | PADDR(m->mmutop));
    1.21 }
    1.22 
    1.23 void