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Mercurial > hg > plan9front / changeset: bcm, bcm64: fix cache operations for dma and emmc

changeset 7249: 3d3af63a444a
parent 7248: d702de816ecf
child 7250: 5ddd42593f0b
author: cinap_lenrek@felloff.net
date: Sun, 19 May 2019 16:54:50 +0200
files: sys/src/9/bcm/dma.c sys/src/9/bcm/emmc.c
description: bcm, bcm64: fix cache operations for dma and emmc

always clean AND invalidate caches before dma read,
never just invalidate as the buffer might not be
aligned to cache lines...

we have to invalidate caches again *AFTER* the dma
read has completed. the processor can bring in data
speculatively into the cache while the dma in in
flight.
     1.1--- a/sys/src/9/bcm/dma.c
     1.2+++ b/sys/src/9/bcm/dma.c
     1.3@@ -170,7 +170,7 @@ dmastart(int chan, int dev, int dir, voi
     1.4 	ti = 0;
     1.5 	switch(dir){
     1.6 	case DmaD2M:
     1.7-		cachedinvse(dst, len);
     1.8+		cachedwbinvse(dst, len);
     1.9 		ti = Srcdreq | Destinc;
    1.10 		cb->sourcead = dmaioaddr(src);
    1.11 		cb->destad = dmaaddr(dst);
    1.12@@ -183,7 +183,7 @@ dmastart(int chan, int dev, int dir, voi
    1.13 		break;
    1.14 	case DmaM2M:
    1.15 		cachedwbse(src, len);
    1.16-		cachedinvse(dst, len);
    1.17+		cachedwbinvse(dst, len);
    1.18 		ti = Srcinc | Destinc;
    1.19 		cb->sourcead = dmaaddr(src);
    1.20 		cb->destad = dmaaddr(dst);
     2.1--- a/sys/src/9/bcm/emmc.c
     2.2+++ b/sys/src/9/bcm/emmc.c
     2.3@@ -398,6 +398,8 @@ emmcio(int write, uchar *buf, int len)
     2.4 	}
     2.5 	if(i)
     2.6 		WR(Interrupt, i);
     2.7+	if(!write)
     2.8+		cachedinvse(buf, len);
     2.9 	poperror();
    2.10 	okay(0);
    2.11 }