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Mercurial > hg > plan9front / changeset: merge

changeset 6852: c775e38cca81
parent 6847: a41c61303f01
parent 6851: 817828d0da99
child 6853: 8ae0e1edff80
author: cinap_lenrek@felloff.net
date: Sun, 28 Oct 2018 06:17:34 +0100
files:
description: merge
     1.1--- a/sys/src/9/bcm/archbcm2.c
     1.2+++ b/sys/src/9/bcm/archbcm2.c
     1.3@@ -237,7 +237,7 @@ cpustart(int cpu)
     1.4 	mb->clr[cpu].doorbell = 1;
     1.5 	trapinit();
     1.6 	clockinit();
     1.7-	mmuinit1();
     1.8+	mmuinit1(0);
     1.9 	timersinit();
    1.10 	cpuidprint();
    1.11 	archreset();
     2.1--- a/sys/src/9/bcm/arm.s
     2.2+++ b/sys/src/9/bcm/arm.s
     2.3@@ -40,8 +40,6 @@
     2.4 	MOVW	$0x10000,R3; \
     2.5 	MOVW	R3,(R2)
     2.6 
     2.7-#define PUTC(s)
     2.8-
     2.9 /*
    2.10  * get cpu id, or zero if armv6
    2.11  */
     3.1--- a/sys/src/9/bcm/armv7.s
     3.2+++ b/sys/src/9/bcm/armv7.s
     3.3@@ -46,6 +46,17 @@ TEXT armstart(SB), 1, $-4
     3.4 	BARRIERS
     3.5 
     3.6 	/*
     3.7+	 * turn SMP on
     3.8+	 * invalidate tlb
     3.9+	 */
    3.10+	MRC	CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
    3.11+	ORR	$CpACsmp, R1		/* turn SMP on */
    3.12+	MCR	CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
    3.13+	BARRIERS
    3.14+	MCR	CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
    3.15+	BARRIERS
    3.16+
    3.17+	/*
    3.18 	 * clear mach and page tables
    3.19 	 */
    3.20 	MOVW	$PADDR(MACHADDR), R1
    3.21@@ -57,17 +68,6 @@ TEXT armstart(SB), 1, $-4
    3.22 	BNE	_ramZ
    3.23 
    3.24 	/*
    3.25-	 * turn SMP on
    3.26-	 * invalidate tlb
    3.27-	 */
    3.28-	MRC	CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
    3.29-	ORR	$CpACsmp, R1		/* turn SMP on */
    3.30-	MCR	CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
    3.31-	BARRIERS
    3.32-	MCR	CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
    3.33-	BARRIERS
    3.34-
    3.35-	/*
    3.36 	 * start stack at top of mach (physical addr)
    3.37 	 * set up page tables for kernel
    3.38 	 */
    3.39@@ -96,7 +96,6 @@ TEXT armstart(SB), 1, $-4
    3.40 	/*
    3.41 	 * enable caches, mmu, and high vectors
    3.42 	 */
    3.43-
    3.44 	MRC	CpSC, 0, R0, C(CpCONTROL), C(0), CpMainctl
    3.45 	ORR	$(CpChv|CpCdcache|CpCicache|CpCmmu), R0
    3.46 	MCR	CpSC, 0, R0, C(CpCONTROL), C(0), CpMainctl
     4.1--- a/sys/src/9/bcm/cache.v7.s
     4.2+++ b/sys/src/9/bcm/cache.v7.s
     4.3@@ -132,17 +132,6 @@ TEXT l2cacheuinv(SB), $-4
     4.4 	MOVW.P	8(R13), R15
     4.5 
     4.6 /*
     4.7- * these shift values are for the Cortex-A8 L1 cache (A=2, L=6) and
     4.8- * the Cortex-A8 L2 cache (A=3, L=6).
     4.9- * A = log2(# of ways), L = log2(bytes per cache line).
    4.10- * see armv7 arch ref p. 1403.
    4.11- */
    4.12-#define L1WAYSH 30
    4.13-#define L1SETSH 6
    4.14-#define L2WAYSH 29
    4.15-#define L2SETSH 6
    4.16-
    4.17-/*
    4.18  * callers are assumed to be the above l1 and l2 ops.
    4.19  * R0 is the function to call in the innermost loop.
    4.20  * R8 is the cache level (one-origin: 1 or 2).
    4.21@@ -184,11 +173,12 @@ TEXT wholecache+0(SB), $-4
    4.22 	ADD	$1, R2		/* R2 (sets) = ((R0 >> 13) & MASK(15)) + 1 */
    4.23 
    4.24 	/* precompute set/way shifts for inner loop */
    4.25+	MOVW	$6, R4
    4.26 	CMP	$0, R8		/* cache == 1? */
    4.27-	MOVW.EQ	$L1WAYSH, R3 	/* yes */
    4.28-	MOVW.EQ	$L1SETSH, R4
    4.29-	MOVW.NE	$L2WAYSH, R3	/* no */
    4.30-	MOVW.NE	$L2SETSH, R4
    4.31+	MOVW.EQ	$30, R3 	/* l1 */
    4.32+	MOVW.NE	$29, R3		/* l2 */
    4.33+	CMP	$16, R5		/* armv8 has 16-way l2, adjust shift */
    4.34+	MOVW.EQ	$28, R3
    4.35 
    4.36 	/* iterate over ways */
    4.37 	MOVW	$0, R7		/* R7: way */
     5.1--- a/sys/src/9/bcm/clock.c
     5.2+++ b/sys/src/9/bcm/clock.c
     5.3@@ -98,7 +98,7 @@ localclockintr(Ureg *ureg, void *)
     5.4 {
     5.5 	if(m->machno == 0)
     5.6 		panic("cpu0: Unexpected local generic timer interrupt");
     5.7-	cpwrsc(0, CpTIMER, CpTIMERphys, CpTIMERphysctl, Imask|Enable);
     5.8+	cpwrsc(0, CpTIMER, CpTIMERphys, CpTIMERphysctl, Imask);
     5.9 	timerintr(ureg, 0);
    5.10 }
    5.11 
    5.12@@ -109,10 +109,6 @@ clockshutdown(void)
    5.13 
    5.14 	tm = (Armtimer*)ARMTIMER;
    5.15 	tm->ctl = 0;
    5.16-	if(cpuserver)
    5.17-		wdogfeed();
    5.18-	else
    5.19-		wdogoff();
    5.20 }
    5.21 
    5.22 void
    5.23@@ -125,10 +121,11 @@ clockinit(void)
    5.24 	if(((cprdsc(0, CpID, CpIDfeat, 1) >> 16) & 0xF) != 0) {
    5.25 		/* generic timer supported */
    5.26 		if(m->machno == 0){
    5.27-			*(ulong*)(ARMLOCAL + Localctl) = 0;				/* input clock is 19.2Mhz crystal */
    5.28+			*(ulong*)(ARMLOCAL + Localctl) = 0;		/* input clock is 19.2Mhz crystal */
    5.29 			*(ulong*)(ARMLOCAL + Prescaler) = 0x06aaaaab;	/* divide by (2^31/Prescaler) for 1Mhz */
    5.30 		}
    5.31 		cpwrsc(0, CpTIMER, CpTIMERphys, CpTIMERphysctl, Imask);
    5.32+		intrenable(IRQcntpns, localclockintr, nil, 0, "clock");
    5.33 	}
    5.34 
    5.35 	tn = (Systimers*)SYSTIMERS;
    5.36@@ -150,8 +147,7 @@ clockinit(void)
    5.37 		tm->load = 0;
    5.38 		tm->ctl = TmrPrescale1|CntEnable|CntWidth32;
    5.39 		intrenable(IRQtimer3, clockintr, nil, 0, "clock");
    5.40-	}else
    5.41-		intrenable(IRQcntpns, localclockintr, nil, 0, "clock");
    5.42+	}
    5.43 }
    5.44 
    5.45 void
    5.46@@ -230,14 +226,10 @@ ulong
    5.47 void
    5.48 microdelay(int n)
    5.49 {
    5.50-	Systimers *tn;
    5.51-	u32int now, diff;
    5.52+	ulong now;
    5.53 
    5.54-	diff = n + 1;
    5.55-	tn = (Systimers*)SYSTIMERS;
    5.56-	now = tn->clo;
    5.57-	while(tn->clo - now < diff)
    5.58-		;
    5.59+	now = µs();
    5.60+	while(µs() - now < n);
    5.61 }
    5.62 
    5.63 void
     6.1--- a/sys/src/9/bcm/fns.h
     6.2+++ b/sys/src/9/bcm/fns.h
     6.3@@ -66,7 +66,7 @@ extern int isaconfig(char*, int, ISAConf
     6.4 extern void l2cacheuwbinv(void);
     6.5 extern void links(void);
     6.6 extern void mmuinit(void*);
     6.7-extern void mmuinit1(void);
     6.8+extern void mmuinit1(int);
     6.9 extern void mmuinvalidate(void);
    6.10 extern void mmuinvalidateaddr(u32int);
    6.11 extern uintptr mmukmap(uintptr, uintptr, usize);
     7.1--- a/sys/src/9/bcm/main.c
     7.2+++ b/sys/src/9/bcm/main.c
     7.3@@ -19,7 +19,7 @@
     7.4  * Where configuration info is left for the loaded programme.
     7.5  */
     7.6 #define BOOTARGS	((char*)CONFADDR)
     7.7-#define	BOOTARGSLEN	(MACHADDR-CONFADDR)
     7.8+#define	BOOTARGSLEN	(REBOOTADDR-PADDR(CONFADDR))
     7.9 #define	MAXCONF		64
    7.10 #define MAXCONFLINE	160
    7.11 
    7.12@@ -301,7 +301,7 @@ main(void)
    7.13 	pageinit();
    7.14 	userinit();
    7.15 	launchinit();
    7.16-	mmuinit1();
    7.17+	mmuinit1(0);
    7.18 	schedinit();
    7.19 	assert(0);			/* shouldn't have returned */
    7.20 }
    7.21@@ -550,6 +550,35 @@ confinit(void)
    7.22 
    7.23 }
    7.24 
    7.25+static void
    7.26+rebootjump(ulong entry, ulong code, ulong size)
    7.27+{
    7.28+	static void (*f)(ulong, ulong, ulong);
    7.29+	static Lock lk;
    7.30+
    7.31+	intrsoff();
    7.32+	intrcpushutdown();
    7.33+
    7.34+	/* redo identity map */
    7.35+	mmuinit1(1);
    7.36+
    7.37+	lock(&lk);
    7.38+	if(f == nil){
    7.39+		/* setup reboot trampoline function */
    7.40+		f = (void*)REBOOTADDR;
    7.41+		memmove(f, rebootcode, sizeof(rebootcode));
    7.42+		cachedwbse(f, sizeof(rebootcode));
    7.43+	}
    7.44+	unlock(&lk);
    7.45+
    7.46+	cacheuwbinv();
    7.47+	l2cacheuwbinv();
    7.48+
    7.49+	(*f)(entry, code, size);
    7.50+
    7.51+	for(;;);
    7.52+}
    7.53+
    7.54 /*
    7.55  *  exit kernel either on a panic or user request
    7.56  */
    7.57@@ -558,14 +587,8 @@ exit(int)
    7.58 {
    7.59 	cpushutdown();
    7.60 	splfhi();
    7.61-	if(m->machno != 0){
    7.62-		void (*f)(ulong, ulong, ulong) = (void*)REBOOTADDR;
    7.63-		intrsoff();
    7.64-		intrcpushutdown();
    7.65-		cacheuwbinv();
    7.66-		(*f)(0, 0, 0);
    7.67-		for(;;);
    7.68-	}
    7.69+	if(m->machno != 0)
    7.70+		rebootjump(0, 0, 0);
    7.71 	archreboot();
    7.72 }
    7.73 
    7.74@@ -585,21 +608,14 @@ isaconfig(char *, int, ISAConf *)
    7.75 void
    7.76 reboot(void *entry, void *code, ulong size)
    7.77 {
    7.78-	void (*f)(ulong, ulong, ulong);
    7.79-
    7.80 	writeconf();
    7.81 	if (m->machno != 0) {
    7.82 		procwired(up, 0);
    7.83 		sched();
    7.84 	}
    7.85 
    7.86-	/* setup reboot trampoline function */
    7.87-	f = (void*)REBOOTADDR;
    7.88-	memmove(f, rebootcode, sizeof(rebootcode));
    7.89-	cachedwbse(f, sizeof(rebootcode));
    7.90-
    7.91 	cpushutdown();
    7.92-	delay(500);
    7.93+	delay(1000);
    7.94 
    7.95 	splfhi();
    7.96 
    7.97@@ -611,14 +627,10 @@ reboot(void *entry, void *code, ulong si
    7.98 
    7.99 	/* stop the clock (and watchdog if any) */
   7.100 	clockshutdown();
   7.101-	intrsoff();
   7.102-	intrcpushutdown();
   7.103-
   7.104-	cacheuwbinv();
   7.105-	l2cacheuwbinv();
   7.106+	wdogoff();
   7.107 
   7.108 	/* off we go - never to return */
   7.109-	(*f)(PADDR(entry), PADDR(code), size);
   7.110+	rebootjump(PADDR(entry), PADDR(code), size);
   7.111 }
   7.112 
   7.113 void
     8.1--- a/sys/src/9/bcm/mem.h
     8.2+++ b/sys/src/9/bcm/mem.h
     8.3@@ -44,6 +44,7 @@
     8.4 #define	KSEGM		0xC0000000
     8.5 #define	KZERO		KSEG0			/* kernel address space */
     8.6 #define CONFADDR	(KZERO+0x100)		/* unparsed plan9.ini */
     8.7+#define	REBOOTADDR	(0x1c00)		/* reboot code - physical address */
     8.8 #define	MACHADDR	(KZERO+0x2000)		/* Mach structure */
     8.9 #define	L2		(KZERO+0x3000)		/* L2 ptes for vectors etc */
    8.10 #define	VCBUFFER	(KZERO+0x3400)		/* videocore mailbox buffer */
    8.11@@ -62,9 +63,6 @@
    8.12 #define	TSTKTOP		(USTKTOP-USTKSIZE)	/* sysexec temporary stack */
    8.13 #define	TSTKSIZ	 	256
    8.14 
    8.15-/* address at which to copy and execute rebootcode */
    8.16-#define	REBOOTADDR	(KZERO+0x1800)
    8.17-
    8.18 /*
    8.19  * Legacy...
    8.20  */
     9.1--- a/sys/src/9/bcm/mkfile
     9.2+++ b/sys/src/9/bcm/mkfile
     9.3@@ -123,8 +123,8 @@ init.h:D:	../port/initcode.c init9.s
     9.4 
     9.5 reboot.h:D:	rebootcode.s arm.s arm.h mem.h
     9.6 	$AS rebootcode.s
     9.7-	# -lc is only for memmove.  -T arg is PADDR(REBOOTADDR)
     9.8-	$LD -l -s -T0x1800 -R4 -o reboot.out rebootcode.$O -lc
     9.9+	# -lc is only for memmove.  -T arg is REBOOTADDR
    9.10+	$LD -l -s -T0x1c00 -R4 -o reboot.out rebootcode.$O -lc
    9.11 	{echo 'uchar rebootcode[]={'
    9.12 	 xd -1x reboot.out |
    9.13 		sed -e '1,2d' -e 's/^[0-9a-f]+ //' -e 's/ ([0-9a-f][0-9a-f])/0x\1,/g'
    10.1--- a/sys/src/9/bcm/mmu.c
    10.2+++ b/sys/src/9/bcm/mmu.c
    10.3@@ -12,6 +12,7 @@
    10.4 #define L2AP(ap)	l2ap(ap)
    10.5 #define L1ptedramattrs	soc.l1ptedramattrs
    10.6 #define L2ptedramattrs	soc.l2ptedramattrs
    10.7+#define PTEDRAM		(PHYSDRAM|Dom0|L1AP(Krw)|Section|L1ptedramattrs)
    10.8 
    10.9 enum {
   10.10 	L1lo		= UZERO/MiB,		/* L1X(UZERO)? */
   10.11@@ -43,7 +44,7 @@ mmuinit(void *a)
   10.12 	/*
   10.13 	 * identity map first MB of ram so mmu can be enabled
   10.14 	 */
   10.15-	l1[L1X(PHYSDRAM)] = PHYSDRAM|Dom0|L1AP(Krw)|Section|L1ptedramattrs;
   10.16+	l1[L1X(PHYSDRAM)] = PTEDRAM;
   10.17 
   10.18 	/*
   10.19 	 * map i/o registers 
   10.20@@ -65,19 +66,19 @@ mmuinit(void *a)
   10.21 	l2[L2X(va)] = PHYSDRAM|L2AP(Krw)|Small|L2ptedramattrs;
   10.22 }
   10.23 
   10.24+/*
   10.25+ * enable/disable identity map of first MB of ram
   10.26+ */
   10.27 void
   10.28-mmuinit1()
   10.29+mmuinit1(int on)
   10.30 {
   10.31 	PTE *l1;
   10.32 
   10.33 	l1 = m->mmul1;
   10.34-
   10.35-	/*
   10.36-	 * undo identity map of first MB of ram
   10.37-	 */
   10.38-	l1[L1X(PHYSDRAM)] = 0;
   10.39+	l1[L1X(PHYSDRAM)] = on? PTEDRAM: Fault;
   10.40 	cachedwbtlb(&l1[L1X(PHYSDRAM)], sizeof(PTE));
   10.41 	mmuinvalidateaddr(PHYSDRAM);
   10.42+	mmuinvalidate();
   10.43 }
   10.44 
   10.45 static void
    11.1--- a/sys/src/9/bcm/rebootcode.s
    11.2+++ b/sys/src/9/bcm/rebootcode.s
    11.3@@ -3,8 +3,6 @@
    11.4  */
    11.5 #include "arm.s"
    11.6 
    11.7-#define PTEDRAM		(Dom0|L1AP(Krw)|Section)
    11.8-
    11.9 #define WFI	WORD	$0xe320f003	/* wait for interrupt */
   11.10 #define WFE	WORD	$0xe320f002	/* wait for event */
   11.11 
   11.12@@ -26,8 +24,16 @@ TEXT	main(SB), 1, $-4
   11.13 	MOVW	$(PsrDirq|PsrDfiq|PsrMsvc), R1
   11.14 	MOVW	R1, CPSR
   11.15 
   11.16-	/* prepare to turn off mmu  */
   11.17-	BL	cachesoff(SB)
   11.18+	/* turn caches off */
   11.19+	MRC	CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
   11.20+	BIC	$(CpCdcache|CpCicache|CpCpredict), R1
   11.21+	MCR	CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
   11.22+	BARRIERS
   11.23+
   11.24+	/* invalidate icache */
   11.25+	MOVW	$0, R0
   11.26+	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
   11.27+	BARRIERS
   11.28 
   11.29 	/* turn off mmu */
   11.30 	MRC	CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
   11.31@@ -49,7 +55,7 @@ dowfi:
   11.32 	MOVW	$0x40000060, R1
   11.33 	ADD		R2<<2, R1
   11.34 	MOVW	0(R1), R0
   11.35-	AND		$0x10, R0
   11.36+	AND	$0x10, R0
   11.37 	BEQ		dowfi
   11.38 	MOVW	$0x8000, R1
   11.39 	BL		(R1)
   11.40@@ -72,47 +78,3 @@ bootcpu:
   11.41 	ORR	R8,R8
   11.42 	B	(R8)
   11.43 	B	0(PC)
   11.44-
   11.45-/*
   11.46- * turn the caches off, double map PHYSDRAM & KZERO, invalidate TLBs, revert
   11.47- * to tiny addresses.  upon return, it will be safe to turn off the mmu.
   11.48- * clobbers R0-R2, and returns with SP invalid.
   11.49- */
   11.50-TEXT cachesoff(SB), 1, $-4
   11.51-	MOVM.DB.W [R14,R1-R10], (R13)		/* save regs on stack */
   11.52-
   11.53-	/* turn caches off, invalidate icache */
   11.54-	MRC	CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
   11.55-	BIC	$(CpCdcache|CpCicache|CpCpredict), R1
   11.56-	MCR	CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
   11.57-	MOVW	$0, R0
   11.58-	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall
   11.59-
   11.60-	/* invalidate stale TLBs before changing them */
   11.61-	BARRIERS
   11.62-	MOVW	$0, R0
   11.63-	MCR	CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
   11.64-	BARRIERS
   11.65-
   11.66-	/* redo double map of first MiB PHYSDRAM = KZERO */
   11.67-	MOVW	12(R(MACH)), R2		/* m->mmul1 (virtual addr) */
   11.68-	MOVW	$PTEDRAM, R1			/* PTE bits */
   11.69-	MOVW	R1, (R2)
   11.70-	DSB
   11.71-	MCR	CpSC, 0, R2, C(CpCACHE), C(CpCACHEwb), CpCACHEse
   11.72-
   11.73-	/* invalidate stale TLBs again */
   11.74-	BARRIERS
   11.75-	MOVW	$0, R0
   11.76-	MCR	CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
   11.77-	BARRIERS
   11.78-
   11.79-	/* relocate SB and return address to PHYSDRAM addressing */
   11.80-	MOVW	$KSEGM, R1		/* clear segment bits */
   11.81-	BIC	R1, R12			/* adjust SB */
   11.82-	MOVM.IA.W (R13), [R14,R1-R10]		/* restore regs from stack */
   11.83-
   11.84-	MOVW	$KSEGM, R1		/* clear segment bits */
   11.85-	BIC	R1, R14			/* adjust return address */
   11.86-
   11.87-	RET
    12.1--- a/sys/src/9/port/devuart.c
    12.2+++ b/sys/src/9/port/devuart.c
    12.3@@ -318,9 +318,8 @@ uartdrained(void* arg)
    12.4 static void
    12.5 uartdrainoutput(Uart *p)
    12.6 {
    12.7-	if(!p->enabled)
    12.8+	if(!p->enabled || up == nil || !islo())
    12.9 		return;
   12.10-
   12.11 	p->drain = 1;
   12.12 	if(waserror()){
   12.13 		p->drain = 0;