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Mercurial > hg > plan9front / changeset: bcm: fix l2 cache maintenance routines for raspi3 (armv8)

changeset 6849: d340bc23fc98
parent 6848: 30f789aeea6d
child 6850: c3a500ff9c5f
author: cinap_lenrek@felloff.net
date: Sun, 28 Oct 2018 06:05:43 +0100
files: sys/src/9/bcm/cache.v7.s
description: bcm: fix l2 cache maintenance routines for raspi3 (armv8)

armv8 has 16-way l2, so adjust shift for the set-way cache
tag format.
     1.1--- a/sys/src/9/bcm/cache.v7.s
     1.2+++ b/sys/src/9/bcm/cache.v7.s
     1.3@@ -132,17 +132,6 @@ TEXT l2cacheuinv(SB), $-4
     1.4 	MOVW.P	8(R13), R15
     1.5 
     1.6 /*
     1.7- * these shift values are for the Cortex-A8 L1 cache (A=2, L=6) and
     1.8- * the Cortex-A8 L2 cache (A=3, L=6).
     1.9- * A = log2(# of ways), L = log2(bytes per cache line).
    1.10- * see armv7 arch ref p. 1403.
    1.11- */
    1.12-#define L1WAYSH 30
    1.13-#define L1SETSH 6
    1.14-#define L2WAYSH 29
    1.15-#define L2SETSH 6
    1.16-
    1.17-/*
    1.18  * callers are assumed to be the above l1 and l2 ops.
    1.19  * R0 is the function to call in the innermost loop.
    1.20  * R8 is the cache level (one-origin: 1 or 2).
    1.21@@ -184,11 +173,12 @@ TEXT wholecache+0(SB), $-4
    1.22 	ADD	$1, R2		/* R2 (sets) = ((R0 >> 13) & MASK(15)) + 1 */
    1.23 
    1.24 	/* precompute set/way shifts for inner loop */
    1.25+	MOVW	$6, R4
    1.26 	CMP	$0, R8		/* cache == 1? */
    1.27-	MOVW.EQ	$L1WAYSH, R3 	/* yes */
    1.28-	MOVW.EQ	$L1SETSH, R4
    1.29-	MOVW.NE	$L2WAYSH, R3	/* no */
    1.30-	MOVW.NE	$L2SETSH, R4
    1.31+	MOVW.EQ	$30, R3 	/* l1 */
    1.32+	MOVW.NE	$29, R3		/* l2 */
    1.33+	CMP	$16, R5		/* armv8 has 16-way l2, adjust shift */
    1.34+	MOVW.EQ	$28, R3
    1.35 
    1.36 	/* iterate over ways */
    1.37 	MOVW	$0, R7		/* R7: way */